Many DC to DC converters may be conceptualized by the circuit illustrated in FIG. 1, where electrical power from a source having a supply voltage VIN is provided to load 102 such that the load voltage is regulated to some voltage less than VIN. A feedback path is provided from node 103 to controller 104, where controller 104 controls the duty cycle of high-side switch 106 and low-side switch 108 to regulate the load voltage. A second-order low pass filter comprising inductor 110 and capacitor 112 couples load 102 to switch point 114 so as to smooth output ripples.
The operating principles for the circuit of FIG. 1 are well known to those skilled in the art of power converters, and need not be repeated here. However, the circuit of FIG. 1 serves as a focal point for discussing some of the issues facing circuit designers. One such issue is the resistance of switches 106 and 108 when they are switched on, which may be termed an on-resistance. In particular, modern microprocessors and other low-power circuits require relatively low regulated supply voltages, so that the duty cycle for low-side switch 108 is larger than the duty cycle for switch 106. As a result, with lower and lower load voltages, the on-resistance of switch 108 may be critical if wasted power is to be minimized. The resistance of the bond wires to switches 106 and 108 also should to be factored in with their on-resistances when considering the power loss due to heat dissipation.
In practice, switches 106 and 108 are realized as power MOSFETs (Metal-Oxide-Semiconductor-Field-Effect-Transistor), where each MOSFET comprises a large number of MOSFETs in parallel. As is well known, there may result parasitic NPN transistors for the power MOSFETs, leading to unwanted current flow. This is illustrated in FIG. 2, where MOSFETs 202 and 204 are the high-side and low-side switches, respectively, and the parasitic NPN transistor for MOSFET 204 is illustrated as transistor 206. For ease of illustration, the feedback path and controller are not shown in FIG. 2, but drivers for MOSFETs 202 and 204 are abstracted by logic gates 208 and 210 to illustrate so-called break-before-make logic. With break-before-make logic, a control signal at input port 212 switches MOSFETS 202 and 204 on and off so that both cannot be on at the same time.
During the dead-time when both MOSFETs 202 and 204 are off simultaneously, and when the current through inductor 110 is in a direction towards load 102 as indicated by arrow 214, the voltage at switch point 114 may fall below ground to −VBE, where VBE is the turn-on voltage for NPN transistor 206, causing emitter current to flow through transistor 206. This causes an unwanted parasitic substrate injection current, which may affect the performance of other circuits in controller 104. For example, in band-gap circuits used to provide a reference voltage, as well as in other circuits, often spatially separated circuit components need to be matched for good performance. However, injection current may not be uniform among such components, so that they do not exhibit matched performance. This may seriously degrade the overall performance of the DC to DC power converter.
To mitigate the flow of substrate injection current into sensitive circuit components, structures may be formed around the power MOSFETs to collect and return to ground substrate injection current so that very little substrate injection current finds its way to sensitive circuits. These structures are commonly referred to as moats.
Another design issue is that the resistance of the wires from the integrated circuit to the package leads should to be considered when designing for high performance. The length of the wires depends upon the placement and size of various components of the DC to DC power converter circuit, as well as the package type. The cost of silicon has dropped to the point where often a substantial cost of the final product is the package rather than the silicon. Consequently, often a circuit designer must design the circuit for a specific package. This represents a formidable challenge when designing a high performance circuit because the circuit designer is not free to choose the number or relative positions of the package leads. For a specific package, there is no obvious way to optimize the size and placement of the power MOSFETs, moats, and switch points so that the sum of the on-resistance and wire resistance for one or both power MOSFETS is minimized, or near minimum.